Memory system and operating method thereof

ABSTRACT

There are provided a memory system and an operating method thereof. A memory system includes a plurality of memory devices for performing operations, a power consumption profile table storing section for storing a power consumption profile table of power consumption values with respect to times when the memory devices perform the operations, and a processor for deriving a total power consumption value for the plurality of memory devices based on the power consumption profile table, and determining whether to release or hold a queued command based on the derived total power consumption value.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) toKorean patent application number 10-2018-0004023, filed on Jan. 11,2018, which is incorporated herein by reference in its entirety.

BACKGROUND 1. Field of Invention

Various embodiments of the present disclosure relate to a memory systemand an operating method thereof. Particularly, the embodiments relate toa memory system and operating method thereof from which the memorycontroller can determine whether a queued command is to be performed orheld based on power consumption amounts of nonvolatile memory devices.

2. Description of Related Art

A nonvolatile memory device may include a plurality of memory blocks. Inaddition, each memory block may include a plurality of memory cells, andan erase operation may be performed simultaneously on memory cells inone memory block.

When a read operation, a program operation, or an erase operationperformed, the nonvolatile memory device consumes power, the amount ofwhich varies depending on a performance time. As an example, when theread operation is performed, the power consumption amount of thenonvolatile memory may increase at the beginning and then decrease aftera certain time elapses.

A memory system may include a plurality of nonvolatile memory devices.Accordingly, it is necessary for the memory system to control totalpower consumption of such devices to be a certain level or less. A highpeak power consumption in the memory system may deteriorate thereliability of the memory system.

SUMMARY

Embodiments provide a memory system for releasing or holding a queuedcommand according to power consumption of nonvolatile memory devices,and an operating method thereof.

According to an aspect of the present disclosure, there is provided amemory system including a plurality of memory devices configured toperform operations, a power consumption profile table storing sectionconfigured to store a power consumption profile table of powerconsumption values with respect to times when the memory devices performthe operations, and a processor configured to derive a total powerconsumption value for the plurality of memory devices based on the powerconsumption profile table, and determine whether to release or hold aqueued command based on the derived total power consumption value.

According to an aspect of the present disclosure, there is provided amethod for operating a memory system including deriving a total powerconsumption value by summing up power consumption values for memorydevices that perform operations based on a table representing powerconsumption values with respect to times of the operations, deriving apower consumption remaining value by subtracting the total powerconsumption value from a maximum power budget, comparing peak powervalues of the operations with the power consumption remaining value, anddetermining whether a command scan operation of scanning queued commandsis to be performed or held based on the compared result.

According to an aspect of the present disclosure, there is provided amemory system including a plurality of nonvolatile memory devicesconfigured to perform operations, a power consumption profile tablestoring section configured to store power consumption profile tables forthe operations, a flash power consumption management section configuredto derive power consumption values for the nonvolatile memory devices,based on the power consumption profile tables corresponding to theoperations performed by the nonvolatile memory devices, a powerconsumption sum-up section configured to derive a total powerconsumption value by summing up the power consumption values, and acommand scheduler configured to determine whether to release or hold aqueued command by comparing peak power values of the operations with thetotal power consumption value.

According to an aspect of the present disclosure, there is provided amemory system including a plurality of memory devices, and a controllerconfigured to control the memory devices to perform operations, whereinthe controller includes a plurality of power consumption tables havingpower consumption information of the operations pre-measured at setintervals, respectively, wherein the controller releases or holds queuedcommands for subsequent operations based on power consumption of thememory system calculated through the power consumption tables and timesof current operations.

BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments will now be described more fully with reference tothe accompanying drawings; however, elements and features of the presentdisclosure may be configured or arranged differently than shown ordescribed herein. Thus, the present invention is not limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure is thorough and complete and fully conveys thescope of the embodiments to those skilled in the art.

In the drawings, dimensions of the figures may be exaggerated forclarity of illustration. It will be understood that when an element isreferred to as being “between” two elements, it can be the only elementbetween the two elements, or one or more intervening elements may alsobe present. Like reference numerals refer to like elements throughout.

FIG. 1 is a diagram illustrating a memory system according to anembodiment of the present disclosure.

FIG. 2 is a diagram illustrating a memory controller of FIG. 1.

FIG. 3 is a diagram illustrating a memory system according to anotherembodiment of the present disclosure.

FIG. 4 is a diagram illustrating a nonvolatile memory device of FIG.

FIG. 5 is a diagram illustrating a memory block of FIG. 4.

FIG. 6 is a diagram illustrating a super block.

FIG. 7 is a diagram illustrating power consumption amounts with respectto time in a read operation.

FIG. 8 is a diagram illustrating a time interval management sectionaccording to an embodiment of the present disclosure.

FIG. 9 is a diagram illustrating a power consumption profile tablestoring section according to an embodiment of the present disclosure.

FIG. 10 is a diagram illustrating a processor according to an embodimentof the present disclosure.

FIG. 11 is a flowchart illustrating a method for managing peak poweraccording to an embodiment of the present disclosure.

FIG. 12 is a flowchart illustrating a method for managing peak poweraccording to another embodiment of the present disclosure.

FIG. 13 is a diagram illustrating another embodiment of the memorysystem.

FIG. 14 is a diagram illustrating another embodiment of the memorysystem.

FIG. 15 is a diagram illustrating another embodiment of the memorysystem.

FIG. 16 is a diagram illustrating another embodiment of the memorysystem.

DETAILED DESCRIPTION

In the following detailed description, embodiments of the presentdisclosure are shown and described simply by way of example. As thoseskilled in the art would realize, the described embodiments may bemodified in various different ways, all without departing from thespirit or scope of the present disclosure. Accordingly, the drawings anddescription are to be regarded as illustrative in nature and notrestrictive.

Moreover, throughout the specification, reference to “an embodiment” orthe like is not necessarily to only one embodiment, and differentreferences to “an embodiment” or the like are not necessarily to thesame embodiment(s).

In the entire specification, when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the another element or be indirectly connectedor coupled to the another element with one or more intervening elementsinterposed. In addition, when an element is referred to as “including” acomponent, this indicates that the element may further include one ormore other components rather than excluding such component(s), unlessthe context indicates otherwise.

FIG. 1 is a diagram illustrating a memory system according to anembodiment of the present disclosure.

Referring to FIG. 1, the memory system 1000 may include a nonvolatilememory device 1100 that retains stored data even when power is cut off,a buffer memory device 1300 for temporarily storing data, and a memorycontroller 1200 for controlling the nonvolatile memory device 1100 andthe buffer memory device 1300 under the control of a host 2000.

The host 2000 may communicate with the memory system 1000, using atleast one of various communication manners, such as a Universal SerialBus (USB), a Serial AT Attachment (SATA), a High Speed InterChip (HSIC),a Small Computer System Interface (SCSI), Firewire, a PeripheralComponent Interconnection (PCI), a PCI Express (PCIe), a Non VolatileMemory Express (NVMe), a Universal Flash Storage (UFS), a Secure Digital(SD), a MultiMedia card (MMC), an Embedded MMC (eMMC), a Dual In-lineMemory Module (DIMM), a Registered DIMM (RDIMM), a Load Reduced DIMM(LRDIMM), and the like.

The memory controller 1200 may control overall operations of the memorysystem 1000, and control data exchange between the host 2000 and thenonvolatile memory device 1100. For example, the memory controller 1200may program or read data by controlling the nonvolatile memory device1100 in response to a request of the host 2000. Also, the memorycontroller 1200 may store information of main memory blocks andsub-memory blocks, which are included in the nonvolatile memory device1100, and select the nonvolatile memory device 1100 to perform a programoperation on a main memory block or a sub-memory block according to theamount of data loaded for the program operation. In some embodiments,the nonvolatile memory device 1100 may include a flash memory.

The memory controller 1200 may control data exchange between the host2000 and the buffer memory device 1300 or temporarily store system datafor controlling the nonvolatile memory device 1100 in the buffer memorydevice 1300. The buffer memory device 1300 may be used as a workingmemory, a cache memory or a buffer memory of the memory controller 1200.The buffer memory device 1300 may store codes and commands, which areperformed by the memory controller 1200. Also, the buffer memory device1300 may store data processed by the memory controller 1200.

The memory controller 1200 may temporarily store data input from thehost 200 in the buffer memory device 1300 and then transmit such data tothe nonvolatile memory device 1100 to be stored therein. Also, thememory controller 1200 may receive data and a logical address, which areinput from the host 2000, and translate the logical address to aphysical address indicating an area in which data is to be actuallystored in the nonvolatile memory device 1100. Also, the memorycontroller 1200 may store, in the buffer memory 1300, alogical-to-physical address mapping table that establishes a mappingrelationship between the logical address and the physical address.

In some embodiments, the buffer memory device 1300 may include a DoubleData Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), a LowPower Double Data Rate 4 (LPDDR4) SDRAM, a Graphics Double Data Rate(DDDR) SDRAM, a Low Power DDR (LPDDR), a Rambus Dynamic Random AccessMemory (RDRAM), etc.

In some embodiments, the memory system 1000 may not include the buffermemory device 1300, which may be provided separately or its functionsdistributed to one or more other components of the memory system 1000.

FIG. 2 is a diagram illustrating the memory controller of FIG. 1.

Referring to FIG. 2, the memory controller 1200 may include a processor710, a memory buffer 720, an error correction code (ECC) circuit 730, ahost interface 740, a buffer control circuit 750, a flash interface 760,a data randomizer 770, a buffer memory interface 780, and a bus 790.

The bus 790 may be configured to provide channels between components ofthe memory controller 1200.

The processor 710 may control overall operations of the memorycontroller 1200, and perform a logical operation. The processor 710 maycommunicate with the external host 2000 through the host interface 740,and communicate with the nonvolatile memory device 1100 through theflash interface 760. Also, the processor 710 may communicate with thebuffer memory device 1300 through the buffer memory interface 780. Also,the processor 710 may control the memory buffer 720 through the buffercontrol circuit 750. The processor 710 may control an operation of thememory system 1000 by using the memory buffer 720 as a working memory, acache memory or a buffer memory.

The processor 710 may queue a plurality of commands input from the host2000. Such an operation is referred to as a multi-queue. The processor710 may sequentially transfer the plurality of queued commands to thenonvolatile memory device 1100.

The memory buffer 720 may be used as the working memory, the cachememory or the buffer memory of the processor 710. The memory buffer 720may store codes and commands, which are performed by the processor 710.The memory buffer 720 may store data processed by the processor 710. Thememory buffer 720 may include a Static RAM (SRAM) or a Dynamic RAM(DRAM).

The ECC circuit 730 may perform error correction. The ECC circuit 730may perform ECC encoding on data to be written in the nonvolatile memorydevice 1100 through the flash interface 760. The ECC-encoded data may betransferred to the nonvolatile memory device 1100 through the flashinterface 760. The ECC circuit 730 may perform ECC decoding on datareceived from the nonvolatile memory device 1100 through the flashinterface 760. As an example, the ECC circuit 730 may be included as acomponent of the flash interface 760 in the flash interface 760.

The host interface 740 is configured to communicate with the externalhost 2000 under the control of the processor 710. The host interface 740may be configured to communicate with the host 2000, using at least oneof various communication protocols, such as a Universal Serial Bus(USB), a Serial AT Attachment (SATA), a High Speed InterChip (HSIC), aSmall Computer System Interface (SCSI), Firewire, a Peripheral ComponentInterconnection (PCI), a PCI express (PCIe), a Nonvolatile MemoryExpress (NVMe), a Universal Flash Storage (UFS), a Secure Digital (SD),a Mu Media Card (MMC), an Embedded MMC (eMMC), a Dual In-line MemoryModule (DIMM), a Registered DIMM (RDIMM), and a Load Reduced DIMM(LRDIMM).

The buffer control circuit 750 is configured to control the memorybuffer 720 under the control of the processor 710.

The flash interface 760 is configured to communicate with thenonvolatile memory device 1100 under the control of the processor 710.The flash interface 760 may communicate a command, an address, and datawith the nonvolatile memory device 1100 through a channel.

As an example, the memory controller 1200 may not include the memorybuffer 720 and the buffer control circuit 750. In such embodiment, thememory buffer 720 and/or the buffer control circuit 750 may be providedseparately or the functions of one or both may be distributed within thememory controller 1200.

As an example, the processor 710 may control an operation of the memorycontroller 1200 by using codes. The processor 710 may load codes from anonvolatile memory device (e.g., a read only memory (ROM)) provided inthe memory controller 1200. As another example, the processor 710 mayload codes from the nonvolatile memory device 1100 through the flashinterface 760.

The data randomizer 770 may randomize data or de-randomize therandomized data. The data randomizer 770 may perform a data randomizingoperation on data to be written in the nonvolatile memory device 1100through the flash interface 760. The randomized data may be transferredto the nonvolatile memory device 1100 through the flash interface 760.The data randomizer 770 may perform a data de-randomizing operation ondata received from the nonvolatile memory device 1100 through the flashinterface 760. As an example, the data randomizer 770 may be included asa component of the flash interface 760.

As an example, the bus 790 of the memory controller 1200 may be dividedinto a control bus and a data bus. The data bus may be configured totransmit data in the memory controller 1200, and the control bus may beconfigured to transmit control information such as a command and anaddress in the memory controller 1200. The data bus and the control busare separated from each other, and may not interfere or influence witheach other. The data bus may be coupled to the host interface 740, thebuffer control circuit 750, the ECC circuit 730, the flash interface760, and the buffer memory interface 780. The control bus may be coupledto the host interface 740, the processor 710, the buffer control circuitunit 750, the flash interface 760, and the buffer memory interface 780.In some embodiments, the memory controller 1200 may not include thebuffer memory interface 780, which may be provided separately or itsfunctions distributed within the memory controller 1200.

The buffer memory interface 780 may be configured to communicate withthe buffer memory device 1300 under the control of the processor 710.The buffer memory interface 780 may communicate a command, an address,and data with the buffer memory device 1300 through a channel.

FIG. 3 is a diagram illustrating a memory system according to anotherembodiment of the present disclosure. FIG. 3 illustrates a memory system1000 including a plurality of nonvolatile memory devices 1100 coupled toa memory controller 1200 through a plurality of channels CH1 to CHk. Aflash interface 760 may include first to kth channel interfaces 761corresponding to the plurality of channels CH1 to CHk.

Referring to FIG. 3, the memory controller 1200 may communicate with theplurality of nonvolatile memory devices 1100 through the plurality ofchannels CH1 to CHk. Each of the plurality of channels CH1 to CHk may becoupled to a respective one of the plurality of channel is interfaces761. As an example, a first channel CH1 may be coupled to a firstchannel interface 761, a second channel CH2 may be coupled to a secondchannel interface 761, and a kth channel CHk may be coupled to a kthchannel interface 761. Each of the plurality of channels CH1 to CHk maybe coupled to one or more nonvolatile memory devices 1100. In addition,nonvolatile memory devices 1100 coupled to different channels mayoperate independently from each other. In other words, a nonvolatilememory device 1100 coupled to the first channel CH1 and a nonvolatilememory device 1100 coupled to the second channel CH may operateindependently from each other. As an example, the memory controller 1200may communicate, in parallel, data or a command with the nonvolatilememory device 1100 coupled to the second channel CH2 through the secondchannel CH2 while communicating data or a command with the nonvolatilememory device 1100 coupled to the first channel CH1 through the firstchannel CH1.

Each of the plurality of channels CH1 to CHk may be coupled to aplurality of nonvolatile memory devices 1100. A plurality of nonvolatilememory devices 1100 coupled to one channel may constitute differentways, e.g., Way1, Way2, WayN, where N represents the number ofnonvolatile memory devices 1100 coupled to one channel. That is, firstto Nth nonvolatile memory devices 1100 may be coupled to the firstchannel CH1 to constitute a first way Way1, a second way Way2, up to anNth way WayN. Alternatively, unlike the configuration shown in FIG. 2,two or more nonvolatile memory devices 1100 on the same channel mayconstitute one way Way.

Since the first to Nth nonvolatile memory devices 1100 coupled to thefirst channel CH1 share the first channel CH1, such nonvolatile memorydevices 1100 may not simultaneously communicate data or a command withthe memory controller 1200 but may sequentially communicate data or acommand with the memory controller 1200. Hereinafter, first to Nthnonvolatile memory devices 1100 respectively configuring first to Nthways Way1 to WayN are referred to as first Way1 to Nth WayN nonvolatilememory devices, respectively. In other words, while the memorycontroller 1200 is transmitting data to the first Way1 nonvolatilememory device 1100 of the first channel CH1 through the first channelCH1, the second Way2 to Nth WayN nonvolatile memory devices 1100 of thefirst channel CH1 may not communicate data or a command with the memorycontroller 1200 through the first channel CH1. In other words, while anyone of the first to Nth nonvolatile memory devices 1100 that share thefirst channel CH1 is occupying the first channel CH1, the othernonvolatile memory devices 1100 coupled to the first channel CH1 may notuse the first channel CH1.

However, first Way1 nonvolatile memory device 1100 of the first channelCH1 and a first Way1 nonvolatile memory device 1100 of a second channelCH2 may independently communicate with the memory controller 1200. Inother words, at the same time when the memory controller 1200communicates data with the first Way1 nonvolatile memory device 1100 ofthe first channel CH1 through the first channel CH1 and the firstchannel interface 761, the memory controller 1200 may communicate datawith the first Way1 nonvolatile memory device 1100 of the second channelCH2 through the second channel and the second channel interface 761.

Way1 to WayN memory devices 1100 coupled to one channel CH may perform,in parallel, the same operation mode. As an example, each of thenonvolatile memory devices 1100 coupled to the first channel CH1 mayperform, in parallel, a read operation. As the number of nonvolatilememory devices 1100 that operate in parallel becomes greater, i.e., asthe number of ways coupled to one channel CH becomes greater, the peakpower consumption of the memory system 1000, i.e., the power consumptionat a specific time may become greater.

Nonvolatile memory devices 1100 coupled to different channels CH mayperform different operations. As an example, when each of thenonvolatile memory devices 1100 coupled to the first channel CH1performs, in parallel, a read operation, each of the nonvolatile memorydevices 1100 coupled to the second channel CH2 may perform, in parallel,a program operation. In other words, nonvolatile memory devices coupledto different channels may perform operations independently. In addition,as the number of channels CH that operate in parallel becomes greater,the peak power of the memory system 1000 may become greater.

Nonvolatile memory devices 1100 coupled to the same channel may not beconfigured to perform, in parallel, different operations.

When a large amount of peak power consumption occurs in the memorysystem 1000, the reliability of the memory system 1000 may deteriorate.Therefore, a technique for controlling the magnitude of instantaneouslyconsumed peak power to a certain level or less in design of the memorysystem 1000 may be required.

FIG. 4 is a diagram illustrating the nonvolatile memory device of FIG.1.

Referring to FIG. 4, the nonvolatile memory device 1100 may include amemory cell array 100 for storing data. The nonvolatile memory device1100 may include peripheral circuits 200 configured to perform a programoperation for storing data in the memory cell array 100, a readoperation for outputting the stored data, and an erase operation forerasing the stored data. The nonvolatile memory device 1100 may includecontrol logic 300 for controlling the peripheral circuits 200 under thecontrol of the memory controller (1200 of FIG. 1).

The memory cell array 100 may include at least one memory plane, e.g.,memory planes 101 a and 101 b. Each of the memory planes 101 a and 101 bmay be configured in the same form. A plurality of memory blocks BLK1 toBLKm in the memory plane 101 a or 101 b may be formed to share a pocketp-well.

Each of the memory planes 101 a and 101 b may include a plurality ofmemory blocks BLK1 to BLKm (m is a positive integer). ath local linesLLa and ath bit lines BL1 a to BLna (n is a positive integer) may becoupled to each of the memory blocks BLK1 to BLKm included in the memoryplane 101 a. In addition, bth local lines LLb and bth bit lines BL1 b toBLnb (n is a positive integer) may be coupled to each of the memoryblocks BLK1 to BLKm in the memory plane 101 b.

For example, each of the ath local lines LLa and the bth local lines LLbmay include a first select line, a second select line, and a pluralityof word lines arranged between the first and second select lines. Also,each of the ath local lines LLa and the bth local lines LLb may includedummy lines arranged between the first select line and the word linesand between the second select line and the word lines. Here, the firstselect line may be a source select line, and the second select line maybe a drain select line. For example, each of the ath local lines LLa andthe bth local lines LLb may include word lines, drain and source selectlines, and source lines SL. For example, each of the ath local lines LLaand the bth local lines LLb may further include dummy lines. Forexample, each of the ath local lines LLa and the bth local lines LLb mayfurther include pipe lines.

The ath local lines LLa may be coupled to each of the memory blocks BLK1to BLKm included in the memory plane 101 a, and the ath bit lines BL1 ato BLna may be commonly coupled to the memory blocks BLK1 to BLKmincluded in the memory plane 101 a. In addition, the bth local lines LLbmay be coupled to each of the memory blocks BLK1 to BLKm included in thememory plane 101 b, and the bth bit lines BL1 b to BLnb may be commonlycoupled to the memory blocks BLK1 to BLKm included in the memory plane101 b. The memory blocks BLK1 to BLKm may be implemented in atwo-dimensional or three-dimensional structure. For example, memorycells may be arranged in a direction parallel to a substrate in memoryblocks BLK1 to BLKm having a two-dimensional structure. For example,memory cells may be arranged in a direction vertical to a substrate inmemory blocks BLK1 to BLKm having a three-dimensional structure.

The peripheral circuits 200 may be configured to perform program, read,and erase operations of a selected memory block under the control of thecontrol logic 300. For example, the peripheral circuits 200, under thecontrol of the control logic 300, may supply verify and pass voltages tothe first select line, the second select line, and the word lines,selectively discharge the first select line, the second select line, andthe word lines, and verify memory cells coupled a selected word lineamong the word lines. For example, the peripheral circuits 200 mayinclude a voltage generating circuit 210, a row decoder 220 a coupled tothe memory plane 101 a, a row decoder 220 b coupled to the memory plane101 b, a page buffer group 230 a coupled to the memory plane 101 a, apage buffer group 230 b coupled to the memory plane 101 b, a columndecoder 240, an input/output circuit 250, and a sensing circuit 260.

The voltage generating circuit 210 may generate various operatingvoltages Vop used for program, read, and erase operations in response toan operation signal OP_CMD. Also, the voltage generating circuit 210 mayselectively discharge the local lines LL in response to the operationsignal OP_CMD. For example, the voltage generating circuit 210 maygenerate a program voltage, a verify voltage, pass voltages, a turn-onvoltage, a read voltage, an erase voltage, a source line voltage, andthe like under the control of the control logic 300.

The row decoder 220 a may transfer the operating voltages Vop to the athlocal lines LLa coupled to a memory block included in the selectedmemory plane 101 a in response to a row address RADD. In addition, therow decoder 220 b may transfer the operating voltages Vop to the bthlocal lines LLb coupled to a memory block included in the selectedmemory plane 101 b in response to a row address RADD.

The page buffer group 230 a may include a plurality of page buffers PB1to PBn coupled to the ath bit lines BL1 a to BLna, and the page buffergroup 230 b may include a plurality of page buffers PB1 to PBn coupledto the bth bit lines BL1 b to BLnb. The page buffers PB1 to PBn mayoperate in response to page buffer control signals PBSIGNALS. Forexample, the page buffers PB1 to PBn in the page buffer group 230 a maytemporarily store data received through the ath bit lines BL1 a to BLna,or sense voltages or currents of the ath bit lines BL1 a to BLna in aread or verify operation.

The column decoder 240 may transfer data between the input/outputcircuit 250 and the page buffer groups 230 a and 230 b in response to acolumn address CADD. For example, the column decoder 240 may exchangedata with the page buffers PB1 to PBn in the page buffer group 230 athrough ath data lines DLa, or exchange data with the page buffers PB1to PBn in the page buffer group 230 b through bth data lines DLb. Also,the column decoder 240 may exchange data with the input/output circuit250 through column lines CL.

The input/output circuit 250 may transfer a command CMD and address ADD,which are received from the memory controller (1200 of FIG. 1), to thecontrol logic 300, or exchange data DATA with the column decoder 240.The address ADD may include a row address RADD and a column addressCADD.

The sensing circuit 260, in a read operation and a verify operation, maygenerate a reference current in response to a permission bit VRY_BIT<#>,and output a pass signal PASS or a fail signal FAIL by comparing an athsensing voltage VPBa received from the page buffer group 230 a or a bthsensing voltage VPBb received from the page buffer group 230 b with areference voltage generated by the reference current.

The control logic 300 may control the peripheral circuits 200 byoutputting the operation signal OP_CMD, the row address RADD, the pagebuffer control signals PBSIGNALS, and the permission bit VRY_BIT<#> inresponse to the command CMD and the address ADD. Also, the control logic300 may determine whether the verify operation has passed or failed inresponse to the pass or fail signal PASS or FAIL.

In an operation of the nonvolatile memory device 1100, the memory blocksmay be units of an erase operation. In other words, a plurality ofmemory cells in one memory block are simultaneously erased, and may notbe selectively erased.

A plurality of memory planes 101 a and 101 b in one nonvolatile memorydevice 1100 may perform, in parallel, one operation mode. As an example,when a first memory plane 101 a in a nonvolatile memory device 1100performs a read operation, a second memory plane 101 b included in thenonvolatile memory device 1100 may perform, in parallel, the readoperation. As an example, when the first memory plane 101 a in thenonvolatile memory device 1100 performs a read operation, the secondmemory plane 101 b may not be configured to perform, in parallel, aprogram or erase operation different from the read operation.

As the number of memory planes 101 a and 101 b that operate in parallelbecomes greater, the magnitude of peak power consumption that occurs ineach of the plurality of nonvolatile memory devices 1100 in the memorysystem 1000 becomes greater. Consequently, the peak power consumption ofthe memory system 1000, i.e., the power consumption at a specific timemay become greater.

A plurality of memory blocks BLK1 to BLKm in one memory plane 101 a or101 b may be erased or programmed in parallel. As the number of memoryblocks BLK1 to BLKm that operate in parallel becomes greater, themagnitude of peak power consumption that occurs in each of the pluralityof nonvolatile memory devices 1100 in the memory system 1000 becomesgreater. Consequently, the peak power consumption of the memory system1000, i.e., the power consumption at a specific time may become greater.

As described above, when a large amount of peak power consumption occursin the memory system 1000, the reliability of the memory system 1000 maydeteriorate. Therefore, a technique for controlling the magnitude ofinstantaneously consumed peak power to a certain level or less in designof the memory system 1000 may be required.

FIG. 5 is a diagram illustrating the memory block of FIG. 4.

Referring to FIG. 5, in the memory block BLKm, a plurality of word linesarranged in parallel may be coupled between a first select line and asecond select line. Here, the first select line may be a source selectline SSL, and the second select line may be a drain select line DSL.More specifically, the memory block BLKm may include a plurality ofstrings ST coupled between bit lines BL1 to BLn and a source line SL.The bit lines BL1 to BLn may be coupled to the strings ST, respectively,and the source line SL may be commonly coupled to the strings ST. Thestrings ST may be configured identically to one another, and therefore,a string ST coupled to a first bit line BL1 will be described in detailas an example.

The string ST may include a source select transistor SST, a plurality ofmemory cells F1 to F16, and a drain select transistor DST, which arecoupled in series to each other between the source line SL and the firstbit line BL1. At least one source select transistor SST and at least onedrain select transistor DST may be included in one string ST, and morethan the sixteen memory cells F1 to F16 shown in the drawing may beincluded in one string ST.

A source of the source select transistor SST may be coupled to thesource line SL, and a drain of the drain select transistor DST may becoupled to the first bit line BL1. The memory cells F1 to F16 may becoupled in series between the source select transistor SST and the drainselect transistor DST. Gates of source select transistors SST indifferent strings ST may be coupled to the source select line SSL, gatesof drain select transistors DST in different strings ST may be coupledto the drain select line DSL, gates of the memory cells F1 to F16 indifferent strings ST may be coupled to a plurality of word lines WL1 toWL16. A group of memory cells coupled to the same word line among thememory cells included in different strings ST may be a physical pagePPG. Therefore, physical pages PPG, of which number corresponds to thatof the word lines WL1 to WL16, may be included in the memory block BLKm.

One memory cell may store data of one bit. This is generally called as asingle level cell (SLC). In this case, one physical page PPG may storeone logical page (LPG) data. The one LPG data may include data bits ofwhich number corresponds to that of cells in one physical page PPG. Inaddition, one memory cell may store data of two or more bits. This isgenerally called as a multi-level cell (MLC). In this case, one physicalpage PPG may store two or more LPG data. As another example, one memorycell MC may store data of three bits. This is generally called as atriple-level cell (TLC). In this case, one physical page PPG may storethree LPG data. In addition, one memory cell MC may store data of fourbits. This is generally called as a quadruple-level cell (QLC). In thiscase, one physical page PPG may store four LPG data.

When one memory cell stores data of 2 bits, one physical page PPG mayinclude two pages PG. One page PG may store one LPG data. One memorycell may have any one of a plurality of threshold voltages according todata, and a plurality of pages PG in one physical page PPG may beexpressed by a difference in threshold voltage.

A plurality of memory cells in one memory block BLKm may be driven asSLCs. In other words, a plurality of memory cells included in one memoryblock BLKm may be programmed and read as SLCs. The memory block BLKm maybe referred to as an SLC block. In addition, a plurality of memory cellsin one memory block BLKm may be driven as MLCs. In other words, aplurality of memory cells in one memory block BLKm may be programmed andread as MLCs. The memory block BLKm may be referred to as an MLC block.

A plurality of memory cells in one memory block BLKm may be driven asTLCs. In other words, a plurality of memory cells in one memory blockBLKm may be programmed and read as TLCs. The memory block BLKm may bereferred to as a TLC block. In addition, a plurality of memory cells inone memory block BLKm may be driven as QLCs. In other words, a pluralityof memory cells included in one memory block BLKm may be programmed andread as QLCs. The memory block BLKm may be referred to as a QLC block.

The nonvolatile memory device 1100 may include one or more SLC blocks,one or more MLC blocks, one or more TLC blocks, and one or more QLCblocks.

FIG. 6 is a diagram illustrating a super block.

Referring to FIG. 6, each of a plurality of ways Way1 to WayNconstituting a first channel CH1 may be configured with one or morenonvolatile memory devices 1100. As described above, one nonvolatilememory device 1100 may include a memory cell array 100 for storing data.The memory cell array 100 may include a plurality of memory blocks BLK1to BLKm. An erase operation may be independently performed on each ofthe memory blocks BLK1 to BLKm 110. An erase operation may besimultaneously performed on a plurality of memory cells in one memoryblock.

A super block may be configured with a set of memory blocks selected inthe respective nonvolatile memory devices 1100 constituting differentways on the same channel. In other words, a first super block S_BLK1 maybe configured with a first memory block BLK1 in a first Way1 nonvolatilememory device 1100, a first memory block BLK1 in a second Way2nonvolatile memory device 1100 to a first memory block BLK1 in an NthWayN nonvolatile memory device 1100. In addition, a second super blockS_BLK2 may be configured with a second memory block BLK2 in the firstWay1 nonvolatile memory device 1100, a second memory block BLK2 in thesecond Way2 nonvolatile memory device 1100 to a second Way2 memory blockBLK2 in the Nth WayN nonvolatile memory device 1100. Similarly, an mthsuper block S_BLKm may be configured with an mth memory block BLKm inthe first Way1 nonvolatile memory device 1100, an mth memory block BLKmin the second Way2 nonvolatile memory device 1100 to an mth memory blockBLKm in the Nth WayN nonvolatile memory device 1100.

A plurality of memory blocks in one super block are physically differentmemory blocks, but may logically operate as one memory block. In otherwords, the plurality of memory blocks in the one super block may besimultaneously programmed or erased. The memory system 1000 performs aprogram or erase operation in units of super blocks, thereby improvingthe performance of the program or erase operation. Also, the memorysystem 1000 performs an operation such as garbage collection or wearleveling in units of super blocks, thereby more efficiently managing aplurality of memory blocks.

A read, program or erase operation may be performed in parallel on theplurality of memory blocks in one super block. As the number of memoryblocks that operate in parallel become greater, i.e., as the number ofmemory blocks constituting one super block becomes greater, the peakpower consumption of the memory system 1000, i.e., the power consumptionat a specific time may become greater. In addition, as the number ofchannels CH that operate in parallel becomes greater, the peak power ofthe memory system 1000 may become greater.

When a large amount of peak power consumption occurs in the memorysystem 1000, the reliability of the memory system 1000 may deteriorate.Therefore, a technique for controlling the magnitude of instantaneouslyconsumed peak power to a certain level or less in design of the memorysystem 1000 may be required.

FIG. 7 is a diagram illustrating power consumption amounts with respectto performance time in a read operation.

Referring to FIG. 7, when a read operation is started in the nonvolatilememory device 1100, the voltage generating circuit 210 of thenonvolatile memory device 1100 may first generate a high voltage for theread operation. At this time, a high voltage pump (not shown) in thevoltage generating circuit 210 is operated, and a large amount of powermay be generally consumed in the operation of the high voltage pump.Consequently, a large amount of power consumption may occur in thenonvolatile memory device 1100 when the read operation is started.

After the nonvolatile memory device 1100 generates the high voltage forthe read operation, the nonvolatile memory device 1100 may apply thegenerated high voltage to a word line and precharge a plurality of bitlines with a predetermined voltage magnitude. During performance of theread operation, the nonvolatile memory device 1100 may consume thelargest amount of power when a charging operation is performed on theword and bit lines. As an example, power consumption of about 50 μA mayoccur.

After the charging operation is performed on the word and bit lines, thenonvolatile memory device 1100 may read data stored in a memory cell MCand temporarily store the read data in the page buffer group 230 a or230 b.

The memory system 1000 may store, as a table, power consumption amountswith respect to performance times generated when the nonvolatile memorydevice 1100 performs the read operation. As an example, the memorysystem 1000 may store power consumption amounts with a resolution of 1mA, segmented at time intervals of 5 μs when the nonvolatile memorydevice 1100 performs the read operation. The results may be stored as atable, as shown in FIG. 7. Different time intervals can be used. Forexample, a time interval of 1 μs can be used, in which casecorresponding power consumption amounts with a resolution of 1 mA may bestored. Accordingly, the memory system 1000 can derive, through thetable, power consumption amounts of the nonvolatile memory device 1100with respect to times, without any separate measurement of powerconsumption after a command for the read operation is input to thenonvolatile memory device 1100.

In a program operation and an erase operation, the memory system 1000may store power consumption amounts with respect to times as a table andstore the table. As an example, in the program operation, the powerconsumption amount may be quantified at a time interval different fromthat in the read operation. As an example, in the read operation, thepower consumption amount may be quantified at a time interval of 1 μs.In the program operation, the power consumption amount may be quantifiedat a time interval of 10 μs. The time taken to perform the programoperation may be shorter than that taken to perform the read operation.This is because a change in power consumption amount per unit time inthe program operation may be smaller than that in the read operation.

Also, in the erase operation,the power consumption may be quantified ata time interval different from those in the read operation and theprogram operation. As an example, in the erase operation, the powerconsumption amount may be quantified at a time interval of 200 μs. Thetime taken to perform the erase operation may be shorter than thosetaken to perform the read operation and the program operation. This isbecause a change in power consumption amount per unit time in the eraseoperation may be smaller than that in the read operation or the programoperation.

In addition, the memory system 1000 may store power consumption amountsas a table and manage the table even when an operation performed in thenonvolatile memory device 1100, such as a cache read operation or acache program operation, and data transmission between the nonvolatilememory device 1100 and the memory controller 1200 are simultaneouslyperformed.

FIG. 8 is a diagram illustrating a time interval management sectionaccording to an embodiment of the present disclosure.

Referring to FIG. 8, the memory controller 1200 may include a timeinterval management section 719. In addition, the time intervalmanagement section 719 may include a read time interval managementsection 7191, a program time interval management section 7192, an erasetime interval management section 7193, a cache read time intervalmanagement section 7194, and a cache program time interval managementsection 7195. As another example, the time interval management section719 may be included in the processor 710.

The read time interval management section 7191 may generate and output aread notification signal Tick_RD by counting a time that elapses from apoint of time when the nonvolatile memory device 1100 starts a readoperation. As an example, the read notification signal Tick_RD mayinclude a plurality of voltage pulses. In other words, the readnotification signal Tick_RD may include pulses generated at a set orpredetermined time interval.

As an example, when a read power consumption profile table of a powerconsumption profile table storing section 714 (of FIG. 9) includes apower consumption amount at a first time interval, the read timeinterval management section 7191 may generate and output the readnotification signal Tick_RD including pulses generated at the first timeinterval starting from when the nonvolatile memory device 1100 startsthe read operation.

As another example, the read time interval management section 7191 maygenerate and output the read notification signal Tick_RD includingpulses periodically generated at the first time interval regardless ofwhen the nonvolatile memory device 1100 starts the read operation.

The program time interval management section 7192 may generate andoutput a program notification signal Tick_PGM by counting a time thatelapses from when the nonvolatile memory device 1100 starts a programoperation. As an example, the program notification signal Tick_PGM mayinclude a plurality of voltage pulses. In other words, the programnotification signal Tick_PGM may include pulses generated at a set orpredetermined time interval.

As an example, when a program power consumption profile table of thepower consumption profile table storing section 714 includes a powerconsumption amount at a second time interval, the program time intervalmanagement section 7192 may generate and output the program notificationsignal Tick_PGM including pulses generated at the second time intervalstarting from when the nonvolatile memory device 1100 starts the programoperation.

As another example, the program time interval management section 7192may generate and output the program notification signal Tick_PGMincluding pulses periodically generated at the second time intervalregardless of when the nonvolatile memory device 1100 starts the programoperation.

The second time interval of the pulses in the program notificationsignal Tick_PGM may be greater than the first time interval of thepulses in the read notification signal Tick_RD.

The erase time interval management section 7193 may generate and outputan erase notification signal Tick_ERS by counting a time that elapsesfrom when the nonvolatile memory device 1100 starts an erase operation.As an example, the erase notification signal Tick_ERS may include aplurality of voltage pulses. In other words, the erase notificationsignal Tick_ERS may include pulses generated at a set or predeterminedtime interval.

As an example, when an erase power consumption profile table of thepower consumption profile table storing section 714 includes a powerconsumption amount at a third time interval, the erase time intervalmanagement section 7193 may generate and output the erase notificationsignal Tick_ERS including pulses generated at the third time intervalstarting from when the nonvolatile memory device 1100 starts the eraseoperation.

As another example, the erase time interval management section 7193 maygenerate and output the erase notification signal Tick_ERS includingpulses periodically generated at the third time interval regardless ofwhen the nonvolatile memory device 1100 starts the erase operation.

The third time interval of the pulses included in the erase notificationsignal Tick_ERS may be greater than the first time interval of thepulses in the read notification signal Tick_RD and the second timeinterval of the pulses included in the program notification signalTick_PGM.

The cache read time interval management section 7194 may generate andoutput a cache read notification signal Tick_CacheRD by counting a timethat elapses from when the nonvolatile memory device 1100 starts a cacheread operation. As an example, the cache read notification signalTick_CacheRD may include pulses generated at a set or predetermined timeinterval.

As an example, when a cache read power consumption profile table of thepower consumption profile table storing section 714 includes a powerconsumption amount at a fourth time interval, the cache read timeinterval management section 7194 may generate and output the cache readnotification signal Tick_CacheRD including pulses generated at thefourth time interval from when the nonvolatile memory device 1100 startsthe cache read operation.

The fourth time interval of the pulses included in the cache readnotification signal Tick_CacheRD may be equal to or different from thefirst time interval of the pulses in the read notification signalTick_RD.

As another example, the cache read time interval management section 7194may generate and output the cache read notification signal Tick_CacheRDincluding pulses periodically generated at the fourth time intervalregardless of when the nonvolatile memory device 1100 starts the cacheread operation.

The cache program time interval management section 7195 may generate andoutput a cache program notification signal Tick_CachePGM by counting atime that elapses from when the nonvolatile memory device 1100 starts acache program operation. As an example, the cache program notificationsignal Tick_CachePGM may include a plurality of voltage pulses. In otherwords, the cache program notification signal Tick_CachePGM may includepulses generated at a set or predetermined time interval.

As an example, when a cache program power consumption profile table ofthe power consumption profile table storing section 714 includes a powerconsumption amount at a fifth time interval, the cache program timeinterval management section 7195 may generate and output the cacheprogram notification signal Tick_CachePGM including pulses generated atthe fifth time interval from when the nonvolatile memory device 1100starts the cache program operation.

As another example, the cache program time interval management section7195 may generate and output the cache program notification signalTick_CachePGM including pulses periodically generated at the fifth timeinterval regardless of when the nonvolatile memory device 1100 startsthe cache program operation.

The fifth time interval of the pulses in the cache program notificationsignal Tick_CachePGM may be equal to or different from the second timeinterval of the pulses in the program notification signal Tick_PGM.

The time interval management section 719 may start generating pulses ina notification signal in response to a queue command signal Command_queoutput from the processor 710. As an example, when the queue commandsignal Command_que corresponds to a read command, the time intervalmanagement section 719 may start generating the read notification signalTick_RD pulses at the first time interval. Also, when the queue commandsignal Command_que is a signal corresponding to a program command, thetime interval management section 719 may start generating the programnotification signal Tick_PGM pulses at the second time interval. Also,when the queue command signal Command_que is a signal corresponding toan erase command, the time interval management section 719 may startgenerating the erase notification signal Tick_ERS pulses at the thirdtime interval.

FIG. 9 is a diagram illustrating a power consumption profile tablestoring section according to an embodiment of the present disclosure.

Referring to FIG. 9, the memory controller 1200 may further include apower consumption profile table storing section 714. In addition, thepower consumption profile table storing section 714 may include a readpower consumption profile table, a program power consumption profiletable, an erase power consumption profile table, a cache read powerconsumption profile table, a cache read power consumption profile table,and a cache program power consumption profile table. As another example,the power consumption profile table storing section 714 may be includedin the processor 710.

The read power consumption profile table may represent power consumptionamounts with respect to time periods within a read operation. As anexample, the read power consumption profile table may represent powerconsumption amounts for time periods at a set time interval startingfrom when a command for the read operation is input to the nonvolatilememory device 1100. Also, the read power consumption profile table mayrepresent power consumption amounts consumed by at least one of thememory planes 101 a and 101 b in the nonvolatile memory device 1100.When read operations are simultaneously performed in the plurality ofmemory planes 101 a and 101 b, the processor 710 may derive a powerconsumption amount consumed by the nonvolatile memory device 1100 forone or more intervals by multiplying the corresponding power consumptionamount(s) stored in the read power consumption profile table by thenumber of memory planes 101 a and 101 b in which the read operations areperformed.

As an example, the read power consumption profile table may include apower consumption amount at a first time interval in the read operation.As an example, the first time interval may be 1 μs, and the read powerconsumption profile table may include power consumption amounts for timeperiods of the read operation at the time interval of 1 μs. The powerconsumption profile table storing section 714 may generate and output aread time signal power consumption signal tRD_PWRConsumptioncorresponding to the power consumption amounts with respect to the timeperiods when the nonvolatile memory device 1100 performs the readoperation based on the read power consumption profile table.

The power consumption profile table storing section 714 may generate andoutput the read time power consumption signal tRD_PWRConsumptioncorresponding to the power consumption amounts with respect to the timeperiods during which the nonvolatile memory device 1100 performs theread operation, based on the read notification signal Tick_RD outputfrom the read time interval management section 7191. In other words, thepower consumption profile table storing section 714 may detect a timeperiod of the read operation, based on the read notification signalTick_RD.

The program power consumption profile table may represent powerconsumption amounts with respect to time periods of a program operation.As an example, the program power consumption profile table may representpower consumption amounts, divided into time periods, starting from whena command for the program operation is input to the nonvolatile memorydevice 1100. Also, the program power consumption profile table mayrepresent power consumption of at least one of memory planes 101 a and101 b in the nonvolatile memory device 1100. When program operations aresimultaneously performed in the plurality of memory planes 101 a and 101b, the processor 710 may derive a total power consumption amountconsumed by the nonvolatile memory device 1100 by multiplying a powerconsumption amount for the applicable time period(s) stored in theprogram power consumption profile table by the number of memory planes101 a and 101 b in which the program operations are performed.

As an example, the program power consumption profile table may includepower consumption amounts at a second time interval in the programoperation. As an example, the second time interval may be 10 μs, and theprogram power consumption profile table may include power consumptionamounts of the program operation for time periods at the interval of 10μs. The power consumption profile table storing section 714 may generateand output a program time power consumption signal tPGM_PWRConsumptioncorresponding to the power consumption amounts with respect to timeperiods of the program operation based on the program power consumptionprofile table.

The power consumption profile table storing section 714 may generate andoutput the program time power consumption signal tPGM_PWRConsumptioncorresponding to the power consumption amounts with respect to timeperiods of the program operation based on the program notificationsignal Tick_PGM output from the program time interval management section7192. In other words, the power consumption profile table storingsection 714 may detect a time period of the program operation based onthe program notification signal Tick_PGM.

The erase power consumption profile table may represent powerconsumption amounts with respect to time periods of an erase operation.As an example, the erase power consumption profile table may representpower consumption amounts, divided into time periods, from when acommand for the erase operation is input to the nonvolatile memorydevice 1100. Also, the erase power consumption profile table mayrepresent power consumption amounts consumed by at least one of memoryplanes 101 a and 101 b in the nonvolatile memory device 1100. When eraseoperations are simultaneously performed in the plurality of memoryplanes 101 a and 101 b included in the nonvolatile memory device 1100,the processor 710 may derive a total power consumption amount consumedby the nonvolatile memory device 1100 by multiplying a power consumptionamount for the applicable time period(s) stored in the erase powerconsumption profile table by the number of memory planes 101 a and 101 bin which the erase operations are performed.

As an example, the erase power consumption profile table may includepower consumption amounts at a third time interval in the eraseoperation. As an example, the third time interval may be 200 μs, and theerase power consumption profile table may include a power consumptionamounts of the erase operation divided into time periods of a third timeinterval of 200 μs. The power consumption profile table storing section714 may generate and output an erase time power consumption signaltERS_PWRConsumption corresponding to the power consumption amounts withrespect to time periods of the erase operation based on the erase powerconsumption profile table.

The power consumption profile table storing section 714 may generate andoutput the erase time power consumption signal tERS_PWRConsumptioncorresponding to the power consumption amounts with respect to timeperiods of the erase operation based on the erase notification signalTick_ERS output from the erase time interval management section 7193. Inother words, the power consumption profile table storing section 714 maydetect a time period of the erase operation based on the erasenotification signal Tick_ERS.

The cache read power consumption profile table may represent powerconsumption amounts with respect to time periods of a cache readoperation. In other words, the cache read power consumption profiletable may represent power consumption amounts with respect to timeperiods of an operation of outputting read data stored in the pagebuffer groups 230 a and 230 b to the memory controller 1200 whileinternally performing a read operation.

As an example, the cache read power consumption profile table mayinclude power consumption amounts at a fourth time interval in the cacheread operation. The power consumption profile table storing section 714may generate and output a cache read time power consumption signaltCacheRD_PWRConsumption corresponding to the power consumption amountswith respect to time periods of the cache read operation based on thecache read power consumption profile table. As an example, the fourthtime interval may be equal to or different from the first time interval.

The power consumption profile table storing section 714 may generate andoutput the cache read time power consumption signaltCacheRD_PWRConsumption corresponding to the power consumption amountswith respect to time periods of the cache read operation, based on thecache read notification signal Tick_CacheRD output from the cache readtime interval management section 7194. In other words, the powerconsumption profile table storing section 714 may detect a time periodof the cache read operation based on the cache read notification signalTick_CacheRD.

The cache program power consumption profile table may represent powerconsumption amounts with respect to time periods of a cache programoperation. In other words, the cache program power consumption profiletable may represent power consumption amounts with respect to timeperiods of an operation of latching program data input from the memorycontroller 1200 to the page buffer groups 230 a and 230 b whileinternally performing a program operation.

As an example, the cache program power consumption profile table mayinclude power consumption amounts at a fifth time interval in the cacheread operation. The power consumption profile table storing section 714may generate and output a cache program time power consumption signaltCachePGM_PWRConsumption corresponding to the power consumption amountswith respect to time periods of the cache program operation based on thecache program power consumption profile table. As an example, the fifthtime interval may be equal to or different from the second timeinterval.

The power consumption profile table storing section 714 may generate andoutput the cache program time power consumption signaltCachePGM_PWRConsumption corresponding to the power consumption amountswith respect to time periods of the cache program operation based on thecache program notification signal Tick_CachePGM output from the cacheprogram time interval management section 7195. In other words, the powerconsumption profile table storing section 714 may detect a time periodof the cache program operation based on the cache program notificationsignal Tick_CachePGM,

The power consumption profile table storing section 714 may output aread peak power signal PeakPWR_RD corresponding to the maximum valueamong the power consumption amounts with respect to the time periods ofthe read operation, a program peak power signal PeakPWR_PGMcorresponding to the maximum value among the power consumption amountswith respect to the time periods of the program operation, an erase peakpower signal PeakPWR_ERS corresponding to the maximum value among thepower consumption amounts with respect to the time periods of the eraseoperation, a cache read peak power signal PeakPWR_CacheRD correspondingto the maximum value among the power consumption amounts with respect tothe time periods of the cache read operation, and a cache program peakpower signal PeakPWR_CachePGM corresponding to the maximum value amongthe power consumption amounts with respect to the time periods of thecache program operation. As an example, referring to FIG. 7, thenonvolatile memory device 1100 may consume a peak power of about 50 mAat an elapsed time of 25 μs from the point of time when the nonvolatilememory device 1100 starts the read operation.

The power consumption profile table storing section 714 may generate theread peak power signal PeakPWR_RD, the program peak power signalPeakPWR_PGM, the erase peak power signal PeakPWR_ERS, the cache readpeak power signal PeakPWR_CacheRD, and the cache program peak powersignal PeakPWR_CachePGM, respectively based on the read powerconsumption profile table, the program power consumption profile table,the erase power consumption profile table, the cache read powerconsumption profile table, and the cache program power consumptionprofile table.

FIG. 10 is a diagram illustrating a processor according to an embodimentof the present disclosure.

Referring to FIG. 10, the processor 710 may further include a flashpower consumption management section 711. In addition, the flash powerconsumption management section 711 may include first to kth channelpower consumption management sections 7111 to 711 k.

The first to kth channel power consumption management sections 7111 to711 k may derive power consumption amounts generated from thenonvolatile memory devices 1100 respectively coupled to the first to kthchannel CH1 to CHk. Also, the first to kth channel power consumptionmanagement sections 7111 to 711 k may output first to kth powerconsumption signals PWRConsumption_CH1 to PWRConsumption_CHkcorresponding to the derived power consumption amounts, respectively.

When the nonvolatile memory devices 1100 coupled to the first channelCH1 perform operations, the first channel power consumption managementsection 7111 may calculate a power consumption amount of the nonvolatilememory devices 1100 coupled to the first channel CH1 with respect totime periods, based on the power consumption amounts provided from thepower consumption profile table storing section 714 and an operationtime provided from the time interval management section 719.

As another example, the first channel power consumption managementsection 7111 may calculate a power consumption amount of the nonvolatilememory devices 1100 coupled to the first channel CH1 with respect totime periods based on the power consumption amounts provided from thepower consumption profile table storing section 714 without informationon the time periods provided from the time interval management section719.

The first channel power consumption management section 7111 may derivean amount of power consumption consumed by the nonvolatile memorydevices 1100 coupled to the first channel CH1, based on the number ofways coupled to the first channel CH1, i.e., the number of nonvolatilememory devices 1100 that perform operations in parallel. Also, the firstchannel power consumption management section 7111 may derive a powerconsumption amount of the nonvolatile memory devices 1100 coupled to thefirst channel CH1, based on the number of memory planes 101 a and 101 bthat perform operations in each of the nonvolatile memory devices 1100coupled to the first channel CH1, and generate and output the firstpower consumption signal PWRConsumption_CH1 corresponding to the derivedpower consumption amount.

As another example, the first channel power consumption managementsection 7111 may request the power consumption profile table storingsection 714 for information on a power consumption amount of operationsbeing performed by the nonvolatile memory devices 1100 coupled to thefirst channel CH1 based on the notification signal transferred from thetime interval management section 719, and receive the requestedinformation from the power consumption profile table storing section714. The notification signal may include a read notification signalTick_RD, a program notification signal Tick_PGM, an erase notificationsignal Tick_ERS, a cache read notification signal Tick_CacheRD, and acache program notification signal Tick_CachePGM. The first channel powerconsumption management section 7111 may select any one of the pluralityof notification signals described above, based on the operations beingperformed by the nonvolatile memory devices 1100 coupled to the firstchannel CH1.

As an example, when the nonvolatile memory devices 1100 coupled to thefirst channel CH1 perform read operations, the first channel powerconsumption management section 7111 may derive an amount of powerconsumed by the nonvolatile memory devices 1100 coupled to the firstchannel CH1 with respect to time periods of the read operations, basedon one or more of the power consumption amounts with respect to the timeperiods, which are output from the read power consumption profile tableof the power consumption profile table storing section 714, the numberof nonvolatile memory devices 1100 coupled to the first channel CH1, thenumber of memory planes 101 a and 101 b on which the read operation isperformed in each of the nonvolatile memory devices 1100, and the readnotification signal Tick_RD transferred from the read time intervalmanagement section 7191, and generate and output a first powerconsumption signal PWRConsumption_CH1 corresponding to the derived powerconsumption amount.

As another example, the first channel power consumption managementsection 7111 may request the power consumption profile table storingsection 714 for information on a power consumption amount generated by aread mode being performed at a corresponding time based on the readnotification signal Tick_RD transferred from the read time intervalmanagement section 7191 when the nonvolatile memory devices 1100 coupledto the first channel CH1 is performs the read operation, and receive therequested information from the power consumption profile table storingsection 714. That is, the power consumption profile table storingsection 714 may output the power consumption amount of the currentlyperformed read operation based on the read power consumption profiletable.

Also, the first channel power consumption management section 7111 mayderive a power consumption amount generated by all of the nonvolatilememory devices 1100 coupled to the first channel CH1, based on theinformation transferred from the power consumption profile table storingsection 714, the number of nonvolatile memory devices 1100 coupled tothe first channel CH1, and the number of memory planes 101 a and 101 bon which the read operation is performed in each of the nonvolatilememory devices 1100.

As another example, when the nonvolatile memory devices 1100 coupled tothe first channel CH1 perform program operations, the first channelpower consumption management section 7111 may derive an amount of powerconsumed by the nonvolatile memory devices 1100 coupled to the firstchannel CH1 with respect to time periods of the program operations,based on one or more of the power consumption amounts with respect tosuch times, which are transferred from the program power consumptionprofile table of the power consumption profile table storing section714, the number of nonvolatile memory devices 1100 coupled to the firstchannel CH1, the number of memory planes 101 a and 101 b on which theprogram operation is performed in each of the nonvolatile memory devices1100, and the program notification signal Tick_PGM transferred from theprogram time interval management section 7192, and generate and output afirst power consumption signal PWRConsumption_CH1 corresponding to thederived power consumption.

As another example, the first channel power consumption managementsection 7111 may request the power consumption profile table storingsection 714 for information on a power consumption amount generated by aprogram operation being performed at a corresponding time based on theprogram notification signal Tick_PGM transferred from the program timeinterval management section 7192 when the nonvolatile memory devices1100 coupled to the first channel CH perform the program operation, andreceive the request information from the power consumption profile tablestoring section 714.

Also, the first channel power consumption management section 7111 mayderive a power consumption amount of all of the nonvolatile memorydevices 1110 coupled to the first channel CH1 based on the informationtransferred from the program power consumption profile table of thepower consumption profile table storing section 714, the number ofnonvolatile memory devices coupled to the first channel CH1, and thenumber of memory planes 101 a and 101 b on which the program operationis performed in each of the nonvolatile memory devices 1100.

As another example, when the nonvolatile memory devices 1100 coupled tothe first channel CH1 performs the erase operation, the first channelpower consumption management section 7111 may derive an amount of powerconsumed by the nonvolatile memory devices 1100 coupled to the firstchannel CH1 with respect to time periods of the erase operation based onone or more of the a power consumption amounts with respect to the timeperiods, which is output from the erase power consumption profile tableof the power consumption profile table storing section 714, the numberof nonvolatile memory devices 1100 coupled to the first channel CH1, thenumber of memory blocks on which the erase operation is performed ineach of the nonvolatile memory devices 1100, and the erase notificationsignal Tick_ERS transferred from the erase time interval managementsection 7193, and generate and output a first power consumption signalPWRConsumption_CH1 corresponding to the derived power consumptionamount.

As another example, the first channel power consumption managementsection 7111 may request the power consumption profile table storingsection 714 for information on a power consumption amount generated bythe erase operation with respect to the time based on the erasenotification signal Tick_ERS transferred from the erase time intervalmanagement section 7193 when the nonvolatile memory devices 1100 coupledto the first channel CH1 performs the erase operation, and receive therequested information from the power consumption profile table storingsection 714. The power consumption profile table storing section 714 mayoutput the information based on the erase power consumption profiletable.

Also, the first channel power consumption management section 7111 mayderive a power consumption amount of all of the nonvolatile memorydevices 1100 coupled to the first channel CH1 based on one or more ofthe information output by the power consumption profile table storingsection 714 through the erase power consumption profile table, thenumber of nonvolatile memory devices 1100 coupled to the first channelCH1, and the number of memory blocks on which the erase operation isperformed in each of the nonvolatile memory devices 1100.

As another example, when the nonvolatile memory devices 1100 coupled tothe first channel CH1 perform cache read operations, the first channelpower consumption management section 7111 may derive an amount of powerconsumed by the nonvolatile memory devices 1100 coupled to the firstchannel CH1 with respect to time periods of the cache read operationbased on one or more the a power consumption amounts with respect to thetime periods, which is output from the cache read power consumptionprofile table of the power consumption profile table storing section714, the number of nonvolatile memory devices 1100 coupled to the firstchannel CH1, and the cache read notification signal Tick_CacheRDtransferred from the cache read time interval management section 7194,and generate and output a first power consumption signalPWRConsumption_CH1 corresponding to the derived power consumptionamount.

As another example, when the nonvolatile memory devices 1100 coupled tothe first channel CH1 perform the cache program operations, the firstchannel power consumption management section 7111 may derive an amountof power consumed by the nonvolatile memory devices 1100 coupled to thefirst channel CH1 with respect to time periods based on one or more ofthe a power consumptions with respect to the time periods, which isoutput from the cache program power consumption profile table of thepower consumption profile table storing section 714, the number ofnonvolatile memory devices 1100 coupled to the first channel CH1, andthe cache program notification signal Tick_CachePGM transferred from thecache program time interval management section 7195, and generate andoutput a first power consumption signal PWRConsumption_CH1 correspondingto the derived power consumption amount.

The processor 710 may further include a power consumption sum-up section715. The power consumption sum-up section 715 may sum up powerconsumption values respectively derived from the first to kth channelpower consumption management sections 7111 to 711 k. In other words, thepower consumption sum-up section 715 may derive a total power amountconsumed by the nonvolatile memory devices 1100 in the memory system1000 by summing up power consumption amounts of the nonvolatile memorydevices 1100 coupled to the first to kth channels CH1 to CHk based onthe first to kth power consumption signals PWRConsumption_CH1 toPWRConsumption_CHk respectively output from the first to kth channelpower consumption management sections 7111 to 711 k, and generate andoutput a total power consumption signal Tot_PWRConsumption_DIEcorresponding to the derived total power consumption amount.

The processor 710 may further include a power budget set section 718.The power budget set section 718 may include information on the maximumpower budget to be consumed by the memory system 1000. As an example,the power budget set section 718 may include information on the maximumpower budget to be consumed by all of the nonvolatile memory devices1100 in the memory system 1000, and generate and output a power budgetsignal PWR_Budget corresponding to the information on the maximum powerbudget. When the maximum power budget is imposed, it is necessary forthe memory system 1000 to control the nonvolatile memory devices 1100 tooperate within such budget set by the power budget set section 718.

The processor 710 may further include a system power management section716. The system power management section 716 may derive a powerconsumption remaining value, which represents remaining and availableamount of power for the nonvolatile memory devices 1100, based on thetotal power consumption signal Tot_PWRConsumption_DIE corresponding tothe total amount of power consumed by the nonvolatile memory devices1100, which is output from the power consumption sum-up section 715 andthe power budget signal PWR_Budget corresponding to the maximum powerbudget available to all of the nonvolatile memory devices 1100, which isoutput from the power budget set section 718, and generate and output apower consumption remaining signal PWRConsumption_Remain correspondingto the power consumption remaining value.

As an example, the system power management section 716 may calculate thepower consumption remaining value by subtracting the total amount ofpower consumed by the nonvolatile memory devices 1100, which is outputfrom the power consumption sum-up section 715, from the maximum powerbudget to be consumed by all of the nonvolatile memory devices 1100,which is output from the power budget set section 718. As an example,when the total power consumption signal Tot_PWRConsumption_DIEcorresponding to the total amount of power consumed by the nonvolatilememory devices 1100, which is output from the power consumption sum-upsection 715, represents 450 mA, and the power budget signal PWR_Budgetcorresponding to the maximum power budget to be consumed by all of thenonvolatile memory device 1100, which is output from the power budgetset section 718, represents 500 mA, the system power management section716 may generate and output a power consumption remaining signalPWRConsumption_Remain representing 50 mA.

The processor 710 may further include a command scheduler 717. Inaddition, the command scheduler 717 may include a command queuingsection 7171 and a command scan section 7172.

The command scheduler 717 may receive the read peak power signalPeakPWR_RD corresponding to the maximum power consumption amount of aread operation, the program peak power signal PeakPWR_PGM correspondingto the maximum power consumption amount of a program operation, theerase peak power signal PeakPWR_ERS corresponding to the maximum powerconsumption amount of an erase operation, the cache read peak powersignal PeakPWR_CacheRD corresponding to the maximum power consumptionamount of a cache read operation, and the cache program peak powersignal PeakPWR_CachePGM corresponding to the maximum power consumptionamount of a cache program operation.

The power consumption profile table storing section 714 may generate theread peak power signal PeakPWR_RD, the program peak power signalPeakPWR_PGM, the erase peak power signal PeakPWR_ERS, the cache readpeak power signal PeakPWR_CacheRD, and the cache program peak powersignal PeakPWR_CachePGM, sequentially based on the read powerconsumption profile table, the program power consumption profile table,the erase power consumption profile table, the cache read powerconsumption profile table, and the cache program power consumptionprofile table.

The command queuing section 7171 may queue a plurality of commands inputfrom the host 2000 or a plurality of commands for a house keepingoperation.

The command scan section 7172 may determine whether to release or hold aqueued command based on the power consumption remaining signalPWRConsumption_Remain output from the system power management section716, the read peak power signal PeakPWR_RD, the program peak powersignal PeakPWR_PGM, the erase peak power signal PeakPWR_ERS, the cacheread peak power signal PeakPWR_CacheRD, and the cache program peak powersignal PeakPWR_CachePGM. The queued command may be released as a queuecommand signal Command_que.

As an example, when a value corresponding to the power consumptionremaining signal PWRConsumption_Remain output from the system powermanagement section 716 is 50 mA, and values corresponding to the readpeak power signal PeakPWR_RD, the program peak power signal PeakPWR_PGM,the erase peak power signal PeakPWR_ERS, the cache read peak powersignal PeakPWR_CacheRD, and the cache program peak power signalPeakPWR_CachePGM are 70 mA, 55 mA, 30 mA, 90 mA, and 80 mA,respectively, the command scan section 7172 may release one erasecommand among the queued commands. In this case, the command scansection 7172 may select an erase command by scanning the commands queuedin the command queuing section 7171, and release the selected erasecommand. The erase command released from the command scan section 7172may be transferred to the nonvolatile memory device 1100 through theflash interface 760 to be performed.

When a plurality of erase commands are queued in the command queuingsection 7171 in the above-described example, the command scan section7172 may select an erase command queued first among the queued erasecommands and release the selected erase command.

As an example, when commands queued in the command queuing section 7171are scanned, the command scan section 7172 may perform a command scanoperation in an order of the commands from a command queued first, i.e.,a command that is in a state in which it is queued for the longest timeto commands queued posterior to the command, i.e., in the same directionas the order in which the commands are queued in the command queuingsection 7171. In this case, when a plurality of erase commands arequeued in the command queuing section 7171, the command scan section7172 may select an erase command scanned first among the queued erasecommands and release the selected erase command.

As another example, when a value corresponding to the power consumptionremaining signal PWRConsumption_Remain output from the system powermanagement section 716 is 60 mA, the command scan section 7172 may scana program command or an erase command among the commands queued in thecommand queuing section 7171, and release the scanned command. Asanother example, the command scan section 7172 may select a commandqueued first among program or erase commands, queued by the commandqueuing section 7171, and release the selected command. As anotherexample, when any one of at least one program command or at least oneerase command is to be released, the command scan section 7172 mayselect a command queued first among commands having high orders ofpriority, and release the selected command. As an example, when theprogram command has a higher order of priority than the erase command,the command scan section 7172 may first scan the program command amongthe commands queued in the command queuing section 7171, and scan andrelease the erase command when there is no queued program command. Inthis case, when a plurality of program commands are queued in thecommand queuing section 7171, the command scan section 7172 may select aprogram command queued first among the plurality of program commands andrelease the selected program command. As another example, the commandscan section 7172 may scan commands in an order of the commands from afirst to a last queued command.

As an example, the read command may have the highest order of priority,the program command may have the next highest order of priority, and theerase command may have an order of priority just below that of theprogram command. As an example, the cache read command may have the sameorder of priority as the read command, and the cache program command mayhave the same order of priority as the program command.

As an example, when a value corresponding to the power consumptionremaining signal PWRConsumption_Remain output from the system powermanagement section 716 is 20 mA, and values corresponding to the readpeak power signal PeakPWR_RD, the program peak power signal PeakPWR_PGM,the erase peak power signal PeakPWR_ERS, the cache read peak powersignal PeakPWR_CacheRD, and the cache program peak power signalPeakPWR_CachePGM are 70 mA, 55 mA, 30 mA, 90 mA, and 80 mA,respectively, the command scan section 7172 does not release any commanduntil the value corresponding to the power consumption remaining signalPWRConsumption_Remain becomes a certain level or more but may wait for acertain time.

As described above, the peak power consumed by the memory system 1000can be managed to a certain level or less through a peak powermanagement operation of the processor 710, and the degradation ofperformance of the memory system 1000 can be minimized.

FIG. 11 is a flowchart illustrating a method for managing peak poweraccording to an embodiment of the present disclosure.

Referring to FIG. 11, as an example, a read peak power value generatedwhen the nonvolatile memory device 1100 performs a read operation isgreater than a program peak power value generated when the nonvolatilememory device 1100 performs a program operation, and the program peakpower value is greater than an erase peak power value generated when thenonvolatile memory device 1100 performs an erase operation. In addition,the read operation may have the highest order of priority, the programoperation may have the next highest order of priority, and the eraseoperation may have the lowest order of priority.

Under the above-described conditions, the processor 710 may derive thetotal power consumed by summing up power consumption amounts of thenonvolatile memory devices 1100 at step S901. Then, the processor 710may derive a power consumption remaining value by subtracting the totalpower consumption amount from the maximum power budget at step S902.

When the power consumption remaining value is greater than a read peakpower value (“YES” at step S903, the processor 710 may scan a readcommand having the highest order of priority among queued commands atstep S904. A command scan operation may be performed in the order inwhich the commands are queued.

When the read command scan succeeds (“NO” at step S905), the scannedcommand may be released at step S912. In addition, the nonvolatilememory device 1100 may perform an internal operation, i.e., the readoperation in response to the released command.

When the read command scan fails without any queued read command (“YES”at the step S905), the processor 710 may scan a program command havingthe next highest order of priority among the queued commands at stepS906.

When the program command scan succeeds (“NO” at step S907), the scannedcommand may be released at step S912. In addition, the nonvolatilememory device 1100 may perform an internal operation, i.e., the programoperation in response to the released command.

When the program command scan fails without any queued read command(“YES” at the step S907), the processor 710 may scan an erase commandhaving the highest order of priority among the queued commands at stepS908.

When the erase command scan succeeds (“NO” at step S909), the scannedcommand may be released at step S912. In the nonvolatile memory device1100 may perform an internal operation, i.e., the erase operation inresponse to the released command.

When the erase command scan fails without any queued read command (“YES”at the step S909), the processor 710 may repeat steps S901 to S912.

When the power consumption remaining value is smaller than the read peakpower value (“NO” at the step S903), the power consumption remainingvalue may be compared with the program peak power value. When the powerconsumption remaining value is greater than the program peak power value(“YES” at step S910), the step S906 may be performed.

When the power consumption remaining value is smaller than the programpeak power value (“NO” at the step S910), the power consumptionremaining value may be compared with the erase peak power value. Whenthe power consumption remaining value is greater than the erase peakpower value (“YES” at step S911), the step S908 may be performed. Whenthe power consumption remaining value is smaller than the erase peakpower value (“NO” at the step S911), the steps S901 to S912 may berepeated.

As an example, the steps S905, S910, and S911 may be simultaneouslyperformed.

FIG. 12 is a flowchart illustrating a method for managing peak poweraccording to another embodiment of the present disclosure.

Referring to FIG. 12, as an example, a read peak power value generatedwhen the nonvolatile memory device 1100 performs a read operation isgreater than a program peak power value generated when the nonvolatilememory device 1100 performs a program operation, and the program peakpower value is greater than an erase peak power value generated when thenonvolatile memory device 1100 performs an erase operation. In addition,the read operation may have the highest order of priority, the programoperation may have the next highest order of priority, and the eraseoperation may have the lowest order of priority.

The processor 710 may derive a total power consumption amount by summingup power consumption amounts of the nonvolatile memory devices 1100 atstep S901. Then, the processor 710 may derive a power consumptionremaining value by subtracting the total power consumption amount fromthe maximum power budget at step S902.

When the power consumption remaining value is smaller than the read peakpower value (“NO” at step 903), the step S910 of FIG. 11 may beperformed.

When the power consumption remaining value is greater than the read peakpower value (“YES” at the step S903), the processor 710 may scan a readcommand having the highest order of priority among queued commands atstep S904.

When the read command scan fails (“YES” at step S905), the step S906 ofFIG. 11 may be performed.

When the read command scan succeeds (“NO” at the step S905) and when oneread command is scanned (“NO” at step S1006), the step S912 of FIG. 11may be performed.

When two or more read commands are scanned (“YES” at the step S1006),the processor 710 may select a read command queued first and release theselected read command at step S1007.

In addition, the nonvolatile memory device 1100 may perform an internaloperation, i.e., the read operation in response to the released command.

As another example, the processor 710 may select a program commandqueued first and release the selected program command even when aplurality of program commands are scanned in the step S906 of FIG. 11.Also, the processor 710 may select an erase command queued first andrelease the selected erase command even when a plurality of erasecommands are scanned in the step S908 of FIG. 11.

FIG. 13 is a diagram illustrating another embodiment of the memorysystem.

Referring to FIG. 13, the memory system 30000 may be implemented as acellular phone, a smart phone, a tablet PC, a personal digital assistant(PDA), or a wireless communication device. The memory system 30000 mayinclude a nonvolatile memory device 1100 and a memory controller 1200capable of controlling an operation of the nonvolatile memory device1100. The memory controller 1200 may control a data access operation ofthe nonvolatile memory device 1100, e.g., a program operation, an eraseoperation, or a read operation under the control of a processor 3100.

Data programmed in the nonvolatile memory device 1100 may be outputthrough a display 3200 under the control of the memory controller 1200.

A radio transceiver 3300 may transmit/receive radio signals through anantenna ANT. For example, the radio transceiver 3300 may convert a radiosignal received through the antenna ANT into a signal that can beprocessed by the processor 3100. Therefore, the processor 3100 mayprocess a signal output from the radio transceiver 3300 and transmit theprocessed signal to the memory controller 1200 or the display 3200. Thememory controller 1200 may program the signal processed by the processor3100 in the nonvolatile memory device 1100. Also, the radio transceiver3300 may convert a signal output from the processor 3100 into a radiosignal, and output the converted radio signal to an external devicethrough the antenna ANT. An input device 3400 is a device capable ofinputting a control signal for controlling an operation of the processor3100 or data to be processed by the processor 3100, and may beimplemented as a pointing device such as a touch pad or a computermount, a keypad, or a keyboard. The processor 3100 may control anoperation of the display 3200 such that data output from the memorycontroller 1200, data output from the radio transceiver 3300, or dataoutput from the input device 3400 can be output through the display3200.

In some embodiments, the memory controller 1200 capable of controllingan operation of the nonvolatile memory device 1100 may be implemented asa part of the processor 3100, or be implemented as a chip separate fromthe processor 3100. Also, the memory controller 1200 may be implementedwith the memory controller shown in FIG. 2.

FIG. 14 is a diagram illustrating another embodiment of the memorysystem.

Referring to FIG. 14, the memory system 40000 may be implemented as apersonal computer (PC), a tablet PC, a net-book, an e-reader, a personaldigital assistant (PDA), a portable multimedia player (PMP), an MP3player, or an MP4 player.

The memory system 40000 may include a nonvolatile memory device 1100 anda memory controller 1200 capable of controlling a data processingoperation of the nonvolatile memory device 1100.

The processor 4100 may output data stored in the nonvolatile memorydevice 1100 through a display 4300 according to data input through aninput device 4200. For example, the input device 4200 may be implementedas a pointing device such as a touch pad or a computer mouse, a keypad,or a keyboard.

The processor 4100 may control overall operations of the memory system40000, and control an operation of the memory controller 1200. In someembodiments, the memory controller 1200 capable of controlling anoperation of the nonvolatile memory device 1100 may be implemented as apart of the processor 4100, or be implemented as a chip separate fromthe processor 4100. Also, the memory controller 1200 may be implementedwith the memory controller shown in FIG. 2.

FIG. 15 is a diagram illustrating another embodiment of the memorysystem.

Referring to FIG. 15, the memory system 50000 may be implemented as animage processing device, e.g., a digital camera, a mobile terminalhaving a digital camera attached thereto, a smart phone having a digitalcamera attached thereto, or a tablet PC having a digital camera attachedthereto.

The memory system 50000 may include a nonvolatile memory device 1100 anda memory controller 1200 capable of controlling a data processingoperation of the nonvolatile memory device 1100, e.g., a programoperation, an erase operation, or a read operation.

An image sensor 5200 of the memory system 50000 may convert an opticalimage into digital signals, and the converted digital signals may betransmitted to the processor 5100 or the memory controller 1200. Underthe control of the processor 5100, the converted digital signals may beoutput through a display 5300, or be stored in the nonvolatile memorydevice 1100 through the memory controller 1200. In addition, data storedin the nonvolatile memory device 1100 may be output through the display5300 under the control of the processor 5100 or the memory controller1200.

In some embodiments, the nonvolatile memory controller 1200 capable ofcontrolling an operation of the nonvolatile memory device 1100 may beimplemented as a part of the processor 5100, or be implemented as a chipseparate from the processor 5100. Also, the memory controller 1200 maybe implemented with the memory controller shown in FIG. 2.

FIG. 16 is a diagram illustrating another embodiment of the memorysystem.

Referring to FIG. 16, the memory system 70000 may be implemented as amemory card or a smart card. The memory system 70000 may include anonvolatile memory device 1100, a memory controller 1200, and a cardinterface 7100.

The memory controller 1200 may control data exchange between thenonvolatile memory device 1100 and the card interface 7100. In someembodiments, the card interface 7100 may be a secure digital (SD) cardinterface or a multi-media card (MMC) interface, but the presentdisclosure is not limited thereto. Also, the memory controller 1200 maybe implemented with the memory controller shown in FIG. 2.

The card interface 7100 may interface data exchange between a host 60000and the memory controller 1200 according to a protocol of the host60000. In some embodiments, the card interface 7100 may support auniversal serial bus (USB) protocol and an inter-chip (IC)-USB protocol.Here, the card interface 7100 may mean hardware capable of supporting aprotocol used by the host 60000, software embedded in the hardware, or asignal transmission scheme.

When the memory system 70000 is coupled to a host interface 6200 of thehost 60000 such as a PC, a tablet PC, a digital camera, a digital audioplayer, a cellular phone, console video game hardware, or a digitalset-top box, the host interface 6200 may perform data communication withthe nonvolatile memory device 1100 through the card interface 7100 andthe memory controller 1200 under the control of a microprocessor 6100.

In the memory system according to embodiments of the present disclosure,it is determined whether a queued command is to be performed or held inthe queue for longer so as to manage a large amount of peak powergenerated by nonvolatile memory devices. As a result, the reliability ofthe memory system can be improved, and the degradation of performance ofthe memory system can be minimized.

Various embodiments have been disclosed herein, and although specificterms are employed, they are used and are to be interpreted in a genericand descriptive sense and not for purpose of limitation. In someinstances, as would be apparent to one skilled in the art as of thefiling of the present application, features, characteristics, and/orelements described in connection with a particular embodiment may beused singly or in combination with features, characteristics, and/orelements described in connection with other embodiments unless otherwisespecifically indicated. Accordingly, it will be understood by those ofskill in the art that various changes in form and details may be madewithout departing from the spirit and scope of the present disclosure asset forth in the following claims.

What is claimed is:
 1. A memory system comprising: a plurality of memorydevices configured to perform operations; a power consumption profiletable storing section configured to store a power consumption profiletable of power consumption values with respect to times when the memorydevices perform the operations; and a processor configured to derive atotal power consumption value for the plurality of memory devices basedon the power consumption profile table, and determine whether to releaseor hold a queued command based on the derived total power consumptionvalue.
 2. The memory system of claim 1, wherein the power consumptionprofile table includes a plurality of power consumption profile tablesrespectively corresponding to the operations.
 3. The memory system ofclaim 2, wherein the plurality of power consumption profile tablesinclude a read power consumption profile table and a program powerconsumption profile table, wherein the read power consumption profiletable includes power consumption values of a read operation at a firsttime interval, wherein the program power consumption profile tableincludes power consumption values of a program operation at a secondtime interval, and wherein the first time interval is different from thesecond time interval.
 4. The memory system of claim 3, furthercomprising: a read time interval management section configured to outputa read notification signal at the first time interval; and a programtime interval management section configured to output a programnotification signal at the second time interval.
 5. The memory system ofclaim 2, wherein the processor further includes: a flash powerconsumption management section configured to derive unit powerconsumption values for the respective memory devices that perform theoperations based on the plurality of power consumption profile tables;and a power consumption sum-up section configured to derive the totalpower consumption value by summing up the unit power consumption values.6. The memory system of claim 5, wherein the processor further includes:a command queuing section configured to queue a plurality of commands;and a command scan section configured to select at least one command byscanning the plurality of queued commands based on the total powerconsumption value, and release the selected command.
 7. The memorysystem of claim 6, wherein the processor further includes: a powerbudget set section configured to set a maximum power budget of thememory system; and a system power management section configured toderive a power consumption remaining value based on the maximum powerbudget and the total power consumption value.
 8. The memory system ofclaim 7, wherein the command scan section selects a commandcorresponding to any one of the operations by comparing peak powervalues of the operations in the power consumption profile table with thepower consumption remaining value.
 9. The memory system of claim 8,wherein the operations have different orders of priority, and whereinthe command scan section selects a command corresponding to any one ofthe operations based on the orders of priorities.
 10. The memory systemof claim 8, wherein the command queuing section sequentially queues theplurality of commands, and wherein the command scan section scans theplurality of commands in the order in which the plurality of commandsare queued.
 11. The memory system of claim 8, wherein the command scansection waits for an operation of scanning the plurality of commandswhen the power consumption remaining value is smaller than the peakpower values.
 12. The memory system of claim 6, wherein the plurality ofmemory devices include first memory devices coupled to a first channeland second memory devices coupled to a second channel, wherein the firstmemory devices and the second memory devices perform differentoperations, and wherein the flash power consumption management sectionincludes a first channel power consumption management section and asecond channel power consumption management section, wherein the firstchannel power consumption management section derives a first powerconsumption value for the first memory devices based on an operationperformed by the first memory devices, data corresponding to theoperation performed by the first memory devices in the power consumptionprofile table, and the number of the first memory devices, and whereinthe second channel power consumption management section derives a secondpower consumption value for the second memory devices based on anoperation performed by the second memory devices, data corresponding tothe operation performed by the second memory devices in the powerconsumption profile table, and the number of the second memory devices.13. The memory system of claim 12, wherein the plurality of memorydevices further include third memory devices coupled to a third channel,wherein the power consumption sum-up section derives the total powerconsumption value by summing up the first power consumption value andthe second power consumption value, and wherein, when the third memorydevices are in an idle state, the command scan section releases theselected command to the third memory devices based on the total powerconsumption value.
 14. A method for operating a memory system, themethod comprising: deriving a total power consumption value by summingup power consumption values for memory devices that perform operationsbased on a table representing power consumption values with respect totimes of the operations; deriving a power consumption remaining value bysubtracting the total power consumption value from a maximum powerbudget; comparing peak power values of the operations with the powerconsumption remaining value; and determining whether a command scanoperation of scanning queued commands is to be performed or held basedon the compared result.
 15. The method of claim 14, wherein theoperations have different orders of priority, and wherein the commandscan operation includes a first selection phase of selecting a commandcorresponding to an operation having the highest order of priority amongthe queued commands when the power consumption remaining value isgreater than the peak power values.
 16. The method of claim 15, whereinthe command scan operation further includes a second selection phase ofselecting a command corresponding to an operation having a next highestorder of priority when the command selection in the first selectionphase fails.
 17. The method of claim 14, wherein the command scanoperation selects a command queued first among commands corresponding toan operation having a peak power value smaller than the powerconsumption remaining value.
 18. The method of claim 14, wherein thetable includes a read power consumption profile table and a programpower consumption profile table, wherein the read power consumptionprofile table includes data obtained by selecting a power consumptionvalue generated when at least one of the memory devices performs a readoperation at a first time interval, wherein the program powerconsumption profile table includes data obtained by selecting a powerconsumption value generated when at least one of the memory devicesperforms a program operation at a second time interval, and wherein thefirst time interval is smaller than the second time interval.
 19. Themethod of claim 18, further comprising: generating a read notificationsignal including pulses generated at the first time interval; andgenerating a program notification signal including pulses generated atthe second time interval, wherein the deriving of the total powerconsumption value is performed in response to the pulses of the readnotification signal or the program notification signal.
 20. A memorysystem comprising: a plurality of nonvolatile memory devices configuredto perform operations; a power consumption profile table storing sectionconfigured to store power consumption profile tables for the operations;a flash power consumption management section configured to derive powerconsumption values for the nonvolatile memory devices based on the powerconsumption profile tables corresponding to the operations performed bythe nonvolatile memory devices; a power consumption sum-up sectionconfigured to derive a total power consumption value by summing up thepower consumption values; and a command scheduler configured todetermine whether to release or hold a queued command by comparing peakpower values of the operations with the total power consumption value.